1. Field of the Invention
The present invention relates to a communication control circuit connected to a multiplex transmission line to transmit messages, and more particularly, to a data storing system for the communication control circuit for storing data transmitted and received.
2. Description of the Related Art
This type of communication control circuit is provided at a multiplex node for performing multiplex transmission of data. The multiplex node is comprised of a communication control circuit (LSI) connected to a multiplex transmission line (multiplex bus) consisting of paired wires, etc., a control circuit (CPU) for controlling load devices, and I/O interface (I/F) circuits located between the individual load devices and the CPU.
The LSI has a receiving buffer circuit for storing message data and an identifier (data ID) for identifying the data. When the LSI receives a message from the multiplex bus, it stores the data and the data ID of the message in the receiving buffer circuit, and sends out an interrupt signal to the CPU to request that it read the data in the receiving buffer circuit.
In response to the above-mentioned interrupt, the CPU interrupts its controlling a load device (e.g., a switch or motor) through the I/F circuit, and reads the data ID in the receiving buffer circuit to determine whether the following data is necessary for its station, then carries out an interrupt processing for taking in the above-mentioned data.
However, in the above-mentioned conventional example, each time a message is received, the CPU is interrupted to store the data in a prescribed memory in the CPU, causing high load on the aforementioned CPU when it stores the data.
To solve the aforementioned problem, in another conventional example, a storage circuit such as a RAM, which permits read and write of data, is provided in place of the aforementioned receiving buffer circuit. In this conventional example, the aforementioned storage circuit comprises an ID storage area for registering data IDs, which are allocated in advance to data necessary for the station, a data storage area for storing message data which correspond to the above-mentioned registered data IDs, and a storage area for a read status which indicates whether the CPU has read the data for each of the above-mentioned registered data IDs. The LSI determines whether the data ID of a message received from the multiplex bus is identical to the above-mentioned registered data ID. If the above-mentioned data IDs are found identical, then the data of the above-mentioned received message is stored in a data storage area which corresponds to the data ID. Then, the LSI determines whether the CPU has read the data for each of the aforementioned registered data IDs by the read status. There were some cases where data that has the identical ID to that of the aforementioned data could not be written unless the aforementioned CPU reads the data. In this example, a data storage area is provided for each data ID, and therefore, the LSI is allowed to store only necessary received data in the same manner as it would access a RAM, thus achieving reduced load on the CPU.
In the aforementioned communication control circuit, data storage areas are provided so that they are keyed to the IDs necessary for the station; therefore, the memory capacity is liable to become enormous.